From the course: Learning Verilog for FPGA Development

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The if-else statement

The if-else statement - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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The if-else statement

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- [Instructor] In this example, I'll show you an implementation of a two-to-one multiplexer module like the one you see in this schematic. It has two inputs in a bus named I, one selection input and an output Y. Here is the code for the multiplexer module starting at line 23. It's called mux_2_to_1. Notice that Y is declared as a register because of the way I'm using it in the following lines of code. So the code consists of a single always statement starting at line 29 which is sensitive to changes in the selection input and the input bus I. As with most statements, if the always block applies to more than one line of code, the block must be enclosed between the begin and end keywords as you can see in this example. What will be evaluated whenever sel or I change is an if-then statement. Here we are checking if the selection input is zero. If so, we are saying the input I[0] to the output. Otherwise, we are saying the…

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