From the course: Learning Verilog for FPGA Development

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Gates and primitives

Gates and primitives - FPGA Tutorial

From the course: Learning Verilog for FPGA Development

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Gates and primitives

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- [Narrator] We've already seen gates in some of the previous examples. All of the the basic n-input gates are available in Verilog as primitives. So you don't have to write modules for them. These are the OR, AND, XOR, NOR, NAND and XNOR gates. To instantiate multi-input gates, the syntax goes like this. First you must specify the gate you want, all in lowercase. Next, you may optionally name the instance. And finally, you specify the connections in a port list, enclosed by parenthesis. Where the first port is the output, and the remaining are the inputs. Buffers and inverters are also available as primitives. And they may have any number of outputs. First, you specify the buffer type, either buf or not, with an optional instance name. And then, the veriadic order of ports is slightly different to n-input gates. The last one is the input. And the remaining are all outputs. As you may know, tristate buffers are useful…

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