High-speed architecture of the CABAC probability modeling for H. 265/HEVC encoders
G Pastuszak - 2016 International Conference on Signals and …, 2016 - ieeexplore.ieee.org
2016 International Conference on Signals and Electronic Systems …, 2016•ieeexplore.ieee.org
In hardware video encoders, the throughput of the entropy coding stage can limit the support
of high-quality and high-resolution videos. This paper presents an FPGA-oriented
optimization method which increases the clock frequency of the probability modeling stage
of the multi-symbol Context Adaptive Binary Arithmetic Coder (CABAC). The method
leverages the unary code to represent probability states updated while coding successive
binary symbols directed to the CABAC. Implementation results show that the maximal …
of high-quality and high-resolution videos. This paper presents an FPGA-oriented
optimization method which increases the clock frequency of the probability modeling stage
of the multi-symbol Context Adaptive Binary Arithmetic Coder (CABAC). The method
leverages the unary code to represent probability states updated while coding successive
binary symbols directed to the CABAC. Implementation results show that the maximal …
In hardware video encoders, the throughput of the entropy coding stage can limit the support of high-quality and high-resolution videos. This paper presents an FPGA-oriented optimization method which increases the clock frequency of the probability modeling stage of the multi-symbol Context Adaptive Binary Arithmetic Coder (CABAC). The method leverages the unary code to represent probability states updated while coding successive binary symbols directed to the CABAC. Implementation results show that the maximal frequency can be increased by about 14-19% for designs implemented in FPGA devices.
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